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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 1.2 / sep. 2005 1 200pin unbuffered ddr2 sdram so -dimms based on 1gb 1st ver. this hynix unbuffered slim outline dual in-line memory module(dimm) series consists of 1gb 1st ver. ddr2 sdrams in fine ball grid array(fbga) packages on a 200pin glass-epoxy substrate. this hynix 1gb 1st ver. based unbuffered ddr2 so-dimm series provide a high performance 8 byte inte rface in 67.60mm width form factor of industry standard. it is suitable for easy interchange and addition. features ordering information notes: * : ?m? stands for hynix dual die package(ddp) based module. part name density organization # of drams # of ranks materials hymp112s648-e3/c4/y5 1gb 128mx64 8 1 leaded hymp325s64m*8-e3/c4/y5 2gb 256mx64 16 2 leaded hymp112s64p8-e3/c4/y5 1gb 128mx64 8 1 lead free hymp325s64m*p8-e3/c4/y5 2gb 256mx64 16 2 lead free ? jedec standard double data rate2 synchronous drams (ddr2 sdrams) with 1.8v +/- 0.1v power supply ? all inputs and outputs are compatible with sstl_1.8 interface ?posted cas ? programmable cas latency 3 ,4 ,5 ? ocd (off-chip driver impedance adjustment) and odt (on-die termination) ? fully differential clock operations (ck & ck ) ? programmable burst length 4 / 8 with both sequential and interleave mode ? auto refresh and self refresh supported ? 8192 refresh cycles / 64ms ? serial presence detect with eeprom ? ddr2 sdram package: 68 ball fbga ? 67.60 x 30.00 mm form factor ? lead-free products are rohs compliant
rev. 1.2 / sep. 2005 2 1 200pin unbuffered ddr2 sdram so-dimms speed grade & key parameters address table e3 (ddr2-400) c4 (ddr2-533) y5 (ddr2-667) unit speed@cl3 400 400 400 mbps speed@cl4 400 533 533 mbps speed@cl5 - - 667 mbps cl-trcd-trp 3-3-3 4-4-4 5-5-5 tck density organization ranks sdrams # of drams # of row/bank/column address refresh method 1gb 128m x 64 2 128mb x 8 8 14(a0~a13)/3(ba0~ba2)/10(a0~a9) 8k / 64ms 2gb 256m x 64 2 128mb x 8 16 14(a0~a13)/3(ba0~ba2)/10(a0~a9) 8k / 64ms
rev. 1.2 / sep. 2005 3 1 200pin unbuffered ddr2 sdram so-dimms pin description symbol type polarity pin description ck[1:0], ck [1:0] input cross point the system clock inputs. all adress an comm ands lines are sampled on the cross point of the rising edge of ck and falling edge of ck . a delay locked loop(dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke[1:0] input active high activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s [1:0] input active low enables the associated ddr2 sdram comm and decoder when low and disables the command decoder when high. when the co mmand decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s 0; rank 1 is selected by s 1 ras , cas , we input active low when sampled at the cross point of the rising edge of ck and falling edge of ck , cas , ras and we define the operation to be excecuted by the sdram. ba[2:0] input selects which ddr2 sdram intern al bank of four or eight is activated. odt[1:0] input active high asserts on-die termination for dq, dm, dqs and dqs signals if enab led via the ddr2 sdram mode register. a[9:0], a10/ap, a[15:11] input during a bank activate command cycle, di fines the row address when sampled at the cross point of the rising edge of ck and falling edge of ck . during a read or write com- mand cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high., autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle., ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. dq[63:0] in/out data input/output pins. dm[7:0] input active high the data write masks, associated with one da ta byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dqs[7:0], dqs [7:0] in/out cross point the data strobe, associated with one data byte, sourced whit data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode, the data strobe is sourced by the ddr2 sdrams and is sent at leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs . if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to vss and ddr2 sdram mode registers programmed approriately. v dd , v dd spd,v ss supply power supplies for core, i/o, serial presense detect, and ground for the module. sda in/out this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resister must be connected to v dd t o act as a pull up. scl input this signals is used to clock data into and out of the spd eeprom. a resistor may be connected from scl to vd d to act as a pull up. sa[1:0] input address pins used to select the serial presence detect base address. test in/out the test pin is reserved for bus analysis to ols and is not connected on normal memory modules(sodimms).
rev. 1.2 / sep. 2005 4 1 200pin unbuffered ddr2 sdram so-dimms pin assignment pin location pin no. front side pin no. back side pin no. front side pin no. back side pin no. front side pin no. back side pin no. front side pin no. back side 1 vref 2 vss 51 dqs2 52 dm2 101 a1 102 a0 151 dq42 152 dq46 3 vss 4 dq4 53 vss 54 vss 103 vdd 104 vdd 153 dq43 154 dq47 5 dq0 6 dq5 55 dq18 56 dq22 105 a10/ap 106 ba1 155 vss 156 vss 7 dq1 8 vss 57 dq19 58 dq23 107 ba0 108 ras 157 dq48 158 dq52 9 vss 10 dm0 59 vss 60 vss 109 we 110 s 0 159 dq49 160 dq53 11 dqs 0 12 vss 61 dq24 62 dq28 111 vdd 112 vdd 161 vss 162 vss 13 dqs0 14 dq6 63 dq25 64 dq29 113 cas 114 odt0 163 nc,test 164 ck1 15 vss 16 dq7 65 vss 66 vss 115 nc/s 1 116 a13 165 vss 166 ck 1 17 dq2 18 vss 67 dm3 68 dqs 3 117 vdd 118 vdd 167 dqs 6 168 vss 19 dq3 20 dq12 69 nc 70 dqs3 119 nc/odt1 120 nc 169 dqs6 170 dm6 21 vss 22 dq13 71 vss 72 vss 121 vss 122 vss 171 vss 172 vss 23 dq8 24 vss 73 dq26 74 dq30 123 dq32 124 dq36 173 dq50 174 dq54 25 dq9 26 dm1 75 dq27 76 dq31 125 dq33 126 dq37 175 dq51 176 dq55 27 vss 28 vss 77 vss 78 vss 127 vss 128 vss 177 vss 178 vss 29 dqs 1 30 ck0 79 cke0 80 nc/cke1 129 dqs 4 130 dm4 179 dq56 180 dq60 31 dqs1 32 ck 0 81 vdd 82 vdd 131 dqs4 132 vss 181 dq57 182 dq61 33 vss 34 vss 83 nc 84 nc/a15 133 vss 134 dq38 183 vss 184 vss 35 dq10 36 dq14 85 ba2 86 nc/a14 135 dq34 136 dq39 185 dm7 186 dqs 7 37 dq11 38 dq15 87 vdd 88 vdd 137 dq35 138 vss 187 vss 188 dqs7 39 vss 40 vss 89 a12 90 a11 139 vss 140 dq44 189 dq58 190 vss 41 vss 42 vss 91 a9 92 a7 141 dq40 142 dq45 191 dq59 192 dq62 43 dq16 44 dq20 93 a8 94 a6 143 dq41 144 vss 193 vss 194 dq63 45 dq17 46 dq21 95 vdd 96 vdd 145 vss 146 dqs 5 195 sda 196 vss 47 vss 48 vss 97 a5 98 a4 147 dm5 148 dqs5 197 scl 198 sa0 49 dqs 2 50 nc 99 a3 100 a2 149 vss 150 vss 199 vddspd 200 sa1 front back 1 39 41 199 2 40 200 42
rev. 1.2 / sep. 2005 5 1 200pin unbuffered ddr2 sdram so-dimms functional block diagram 1gb(128mbx64) : hymp112s648-e3/c4 cke0 dqs0 odt0 d0 /c s o d t c k e dqs0 dqs /d q s 0 /d q s dm0 dm dq0 i/o 0 dq1 i/o 1 dq2 i/o 2 dq3 i/o 3 dq4 i/o 4 dq5 i/o 5 dq6 i/o 6 i/o 7 dq7 d1 /c s o d t c k e dqs1 dqs /d q s 1 /d q s dm1 dm dq8 i/o 0 dq8 i/o 1 dq10 i/o 2 dq11 i/o 3 dq12 i/o 4 dq13 i/o 5 dq14 i/o 6 i/o 7 dq15 d2 /c s o d t c k e dqs2 dqs /d q s 2 /d q s dm2 dm dq16 i/o 0 dq17 i/o 1 dq18 i/o 2 dq19 i/o 3 dq20 i/o 4 dq21 i/o 5 dq22 i/o 6 i/o 7 dq23 d3 /c s o d t c k e dqs3 dqs /d q s 3 /d q s dm3 dm dq24 i/o 0 dq25 i/o 1 dq26 i/o 2 dq27 i/o 3 dq28 i/o 4 dq29 i/o 5 dq30 i/o 6 i/o 7 dq31 scl sda a0 a1 a2 serial pd scl sda wp sa0 sa1 d5 /c s o d t c k e dqs5 dqs /d q s 5 /d q s dm5 dm dq40 i/o 0 dq41 i/o 1 dq42 i/o 2 dq43 i/o 3 dq44 i/o 4 dq45 i/o 5 dq46 i/o 6 i/o 7 dq47 d6 /c s o d t c k e dqs6 dqs /d q s 6 /d q s dm6 dm dq48 i/o 0 dq49 i/o 1 dq50 i/o 2 dq51 i/o 3 dq52 i/o 4 dq53 i/o 5 dq54 i/o 6 i/o 7 dq55 d7 /c s o d t c k e dqs0 dqs /d q s 0 /d q s dm0 dm dq56 i/o 0 dq57 i/o 1 dq58 i/o 2 dq59 i/o 3 dq60 i/o 4 dq61 i/o 5 dq62 i/o 6 i/o 7 dq63 d4 /c s o d t c k e dqs4 dqs /d q s 4 /d q s dm4 dm dq32 i/o 0 dq33 i/o 1 dq34 i/o 2 dq35 i/o 3 dq36 i/o 4 dq37 i/o 5 dq38 i/o 6 i/o 7 dq39 /s 1 n.c. odt1 n.c. cke1 n.c. 3 ?+/? 5% ba0-ba2 3 ? +/- 5% a0-an /ras /cas /w e sdrams d0-7 sdrams d0-7 sdrams d0-7 sdrams d0-7 sdrams d0-7 4 loads ck0 /ck0 4 loads ck1 /ck1 1. resistor values are 22 ohm +/- 5%. notes : v dd spd v dd v ref v ss serial pd sdrams do-d7 sdrams do-d7, vdd and vddq sdrams do-d7, spd
rev. 1.2 / sep. 2005 6 1 200pin unbuffered ddr2 sdram so-dimms functional block diagram 2gb(256mbx64) : hymp351s64m8-e3/c4 cke 1 /s1 odt1 scl sda a0 a1 a2 serial pd scl sda wp sa0 sa1 : 3 ?+/? 5% d0,d8(ddp) dqs0 dqs /dqs0 /dqs dm0 dm dq 0 i/ o 0 dq 1 i/ o 1 dq 2 i/ o 2 dq 3 i/ o 3 dq 4 i/ o 4 dq 5 i/ o 5 dq 6 i/ o 6 i/ o 7 dq7 d1,d9( ddp) dqs 1 dqs /dqs1 /dqs dm1 dm dq8 i/ o 0 dq8 i/ o 1 dq 10 i/ o 2 dq 11 i/ o 3 dq 12 i/ o 4 dq 13 i/ o 5 dq 14 i/ o 6 i/ o 7 dq 15 dqs 2 dqs /dqs2 /dqs dm2 dm dq 16 i/ o 0 dq 17 i/ o 1 dq 18 i/ o 2 dq 19 i/ o 3 dq 20 i/ o 4 dq 21 i/ o 5 dq 22 i/ o 6 i/ o 7 dq 23 dqs 3 dqs /dqs3 /dqs dm3 dm dq 24 i/ o 0 dq 25 i/ o 1 dq 26 i/ o 2 dq 27 i/ o 3 dq 28 i/ o 4 dq 29 i/ o 5 dq 30 i/ o 6 i/ o 7 dq 31 dqs 5 dqs /dqs5 /dqs dm 5 dm dq 40 i/ o 0 dq 41 i/ o 1 dq 42 i/ o 2 dq 43 i/ o 3 dq 44 i/ o 4 dq 45 i/ o 5 dq 46 i/ o 6 i/ o 7 dq 47 dqs 6 dqs /dqs6 /dqs dm 6 dm dq 48 i/ o 0 dq 49 i/ o 1 dq 50 i/ o 2 dq 51 i/ o 3 dq 52 i/ o 4 dq 53 i/ o 5 dq 54 i/ o 6 i/ o 7 dq 55 dqs 7 dqs /dqs7 /dqs dm 7 dm dq 56 i/ o 0 dq 57 i/ o 1 dq 58 i/ o 2 dq 59 i/ o 3 dq 60 i/ o 4 dq 61 i/ o 5 dq 62 i/ o 6 i/ o 7 dq 63 dqs 4 dqs /dqs4 /dqs dm 4 dm dq 32 i/ o 0 dq 33 i/ o 1 dq 34 i/ o 2 dq 35 i/ o 3 dq 36 i/ o 4 dq 37 i/ o 5 dq 38 i/ o 6 i/ o 7 dq 39 cke 0 /s0 odt0 /cs 0 odt 0 cke0 /cs 1 odt 1 cke1 / cs 0 odt 0 cke 0 / cs 1 odt 1 cke 1 /cs 0 odt 0 cke0 /cs 1 odt 1 cke1 /cs 0 odt 0 cke0 /cs 1 odt 1 cke1 /cs 0 odt 0 cke0 /cs 1 odt 1 cke1 /cs 0 odt 0 cke0 /cs 1 odt 1 cke1 /cs 0 odt 0 cke0 /cs 1 odt 1 cke1 /cs 0 odt 0 cke0 /cs 1 odt 1 cke1 d2,d10(ddp) d3,d11( ddp) d7,d 15( ddp) d6,d 14( ddp) d5,d 13( ddp) d4,d 12( ddp) 1. resistor values are 22 ohm +/- 5% notes : v dd spd v dd v ref v ss serial pd sdrams do-d 15 sdrams do -d15 , v dd and v dd q sdrams do -d15 , spd ba0 f ba2 10 ? +/-5 % a0-an /ras /cas /we sdrams d 0-15 sdrams d 0-15 sdrams d 0-15 sdrams d 0-15 sdrams d 0-15 8 loads ck0 /ck0 8 loads 9.1 pf 8 loads ck1 /ck1 8 loads 9.1 pf
rev. 1.2 / sep. 2005 7 1 200pin unbuffered ddr2 sdram so-dimms absolute maximum ratings notes: 1. stress greater than those listed may cause permanent dama ge to the device. this is a stress rating only, and device functional operation at or above the conditions indica ted is not implied. expousure to absolute maximum rating con ditions for extended periods may affect reliablility. operating conditions notes: 1. up to 9850 ft. 2. if the dram case temperature is above 85 o c , the auto-refresh command inte rval has to be reduced to trefi=3.9us. for measurement conditions of t case , please refer to the jedec document jesd51-2. dc operating conditions (sstl_1.8) notes: 1. v ddq must be less than or equal to v dd . 2. peak to peak ac noise on v ref may not exeed +/-2% v ref (dc) 3. vtt of transmitting device must track vref of receiving device. parameter symbol value unit note voltage on v dd pin relative to vss v dd - 1.0 v ~ 2.3 v v 1 voltage on vddl pin relative to vss v ddl -0.5v ~ 2.3 v v 1 voltage on v ddq pin relative to vss v ddq - 0.5 v ~ 2.3 v v 1 voltage on any pin relative to vss v in, v out - 0.5 v ~ 2.3 v v 1 storage temperature t stg -50 ~ +100 o c 1 storage humidity(without condensation) h stg 5 to 95 % 1 parameter symbol rating units notes dimm operating temperature(ambient) t opr 0 ~ +55 o c dimm barometric pressure(operating & storage) p bar 105 to 69 k pascal 1 dram component case temperature range t case 0 ~+95 o c 2 parameter symbol min max unit note power supply voltage v dd 1.7 1.9 v v ddl 1.7 1.9 v v ddq 1.7 1.9 v 1 input reference voltage v ref 0.49 x v ddq 0.51 x v ddq v2 eeprom supply voltage v ddspd 1.7 3.6 v termination voltage v tt v ref -0.04 v ref +0.04 v 3
rev. 1.2 / sep. 2005 8 1 200pin unbuffered ddr2 sdram so-dimms input dc logic level input ac logic level ac input test conditions notes : 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising edges and the range from v ref to v il(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switchin g from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. parameter symbol min max unit note input high voltage v ih (dc) v ref + 0.125 v ddq + 0.3 v input low voltage v il (dc) -0.30 v ref - 0.125 v parameter symbol ddr2 400/533 ddr2 667 unit min max min max ac input logic high v ih (ac) v ref + 0.250 - v ref + 0.200 - v ac input logic low v il (ac) -v ref - 0.250 - v ref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr < figure : ac input test signal waveform>
rev. 1.2 / sep. 2005 9 1 200pin unbuffered ddr2 sdram so-dimms differential input ac logic level 1. v in (dc) specifies the allowable dc execution of ea ch input of differential pair such as ck, ck , dqs, dqs , ldqs, ldqs , udqs and udqs . 2. v id (dc) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs or udqs) level and v cp is the complementary input (such as ck , dqs , ldqs or udqs ) level. the minimum value is equal to v ih (dc) - v il (dc). notes : 1. v id (ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih (ac) - v il (ac). 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix (ac) is expected to track variations in v ddq . v ix (ac) indicates the voltage at whitch differential input signals must cross. differential ac ou tput parameters notes: 1. the typical value of v ox (ac) is expected to be about 0.5 * v ddq of the transmitti ng device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at whitch di fferential output signals must cross. symbol parameter min. max. units note v id (ac) ac differential input voltage 0.5 v ddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * v ddq - 0.175 0.5 * v ddq + 0.175 v 2 symbol parameter min. max. units note v ox (ac) ac differential cross point voltage 0.5 * v ddq - 0.125 0.5 * v ddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels >
rev. 1.2 / sep. 2005 10 1 200pin unbuffered ddr2 sdram so-dimms output buffer levels output ac test conditions notes: 1. the vddq of the device under test is referenced. output dc current drive notes: 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh (dc) and i ol (dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating po int along a 21 ohm load line to define a convenient driver current for measurement. symbol parameter sstl_18 units notes v otr output timing measurement reference level 0.5 * v ddq v1 symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4
rev. 1.2 / sep. 2005 11 1 200pin unbuffered ddr2 sdram so-dimms pin capacitance (vdd=1.8v,vddq=1.8v, ta=25 . f=1mhz ) 1gb : hymp112s64[p]8 2gb : hymp351s64m[p]8 notes: 1. pins not under test are tied to gnd. 2. these value are guaranteed by design and tested on a sample basis only. pin symbol min max unit ck, ck cck 13 21 pf cke, odt,cs ci1 24 38 pf address, ras , cas , we ci2 23 40 pf dq, dm, dqs, dqs cio 5 8 pf pin symbol min max unit ck, ck cck 25 49 pf cke, odt,cs ci1 32 58 pf address, ras , cas , we ci2 47 96 pf dq, dm, dqs, dqs cio 16 20 pf
rev. 1.2 / sep. 2005 12 1 200pin unbuffered ddr2 sdram so-dimms idd specifications (t case : 0 to 95 o c ) 1gb, 128m x 64 so- dimm : hymp112s64[p]8 2gb, 256m x 64 so - dimm : hymp325s64m[p]8 notes: 1. idd6 current values are guaranted up to tcase of 85 symbol e3(ddr2 400@cl3) c4(ddr2 533@cl 4) y5(ddr2 667@cl 5) unit note idd0 800 880 960 ma idd1 880 960 1040 ma idd2p 48 48 56 ma idd2q 320 400 480 ma idd2n 360 440 520 ma idd3p(f) 200 240 280 ma idd3p(s) 56 64 72 ma idd3n 480 560 640 ma idd4r 1040 1360 1840 ma idd4w 1120 1440 1920 ma idd5b 2160 2160 2160 ma idd6 64 64 64 ma 1 idd6(l) 40 40 40 ma 1 idd7 1920 2400 2720 ma symbol e3(ddr2 400@cl 3) c4(ddr2 533@cl 4) y5(ddr2 667@cl 5) unit note idd0 1280 1440 1600 ma idd1 1360 1520 1680 ma idd2p 96 96 112 ma idd2q 640 800 960 ma idd2n 720 880 1040 ma idd3p(f) 400 480 560 ma idd3p(s) 112 128 144 ma idd3n 960 1120 1280 ma idd4r 1520 1920 2480 ma idd4w 1760 2080 2560 ma idd5b 2640 2720 2800 ma idd6 128 128 128 ma 1 idd6(l) 80 80 80 ma 1 idd7 2720 3120 3360 ma
rev. 1.2 / sep. 2005 13 1 200pin unbuffered ddr2 sdram so-dimms idd meauarement conditions notes: 1. idd specifications are tested after the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs, udqs, and udqs . idd values must be me t with all combinations of emrs bits 10 and 11. 5. definitions for idd low is defined as vin vilac(max) high is defined as vin vihac(min) stable is defined as inputs st able at a high or low level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between high and low every other clock cy cle (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer ( once per clock) for dq signals not including masks or strobes. symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras- min(idd);cke is high, cs is high between valid commands;address bus inputs are switching;data bus inputs are switching ma idd1 operating one bank active-read-precharge curren ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd) ; cke is high, cs is high between valid commands ; address bus inputs are switching ; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle ; t ck = t ck(idd) ; cke is low ; ot her control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs ar e stable; data bus inputs are float- ing fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current; all banks open, contin uous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid com- mands; address bus inputs are switching;; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. idd6 current values are guaranted up to tcase of 85 max. ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the following page for detailed timing conditions ma
rev. 1.2 / sep. 2005 14 1 200pin unbuffered ddr2 sdram so-dimms electrical characteri stics & ac timings speed bins and cl,trcd,trp,trc and tras for corresponding bin ac timing parameters by speed grade speed ddr2-667 (y5) ddr2-533 (c4) ddr2-400 (e3) unit bin(cl-trcd-trp) 5-5-5 4-4-4 3-3-3 parameter min min min cas latency 5 4 3 tck trcd 15 15 15 ns trp 151515ns tras 45 45 40 ns trc 606055ns parameter symbol ddr2-400 ddr2-533 unit note min max min max data-out edge to clock edge skew tac -600 600 -500 500 ps dqs-out edge to clock edge skew tdqsck -500 500 -450 450 ns clock high level width tch 0.45 0.55 0.45 0.55 ck clock low level width tcl 0.45 0.55 0.45 0.55 ck clock half period thp min (tcl,tch) - min (tcl,tch) -ns system clock cycle time tck 5000 8000 3750 8000 ps dq and dm input setup time tds 150 - 100 - ps 1 dq and dm input hold time tdh 275 - 225 - ps 1 dq and dm input setup time(single-ended strobe) tds1 25 - -25 - ps 1 dq and dm input hold time(single-ended strobe) tdh1 25 - -25 - ps 1 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse witdth for each input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance window from ck, /ck thz - tac max - tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq - 350 -300 ps dq hold skew factor tqhs - 450 -400 ps dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps first dqs latching transition to associated clock edge tdqss -0.25 +0.25 -0.25 +0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck write preamble twpre 0.35 - 0.35 - tck data-out edge to clock edge skew tac -600 600 -500 500 ps address and control input setup time tis 350 -250 - ps
rev. 1.2 / sep. 2005 15 1 200pin unbuffered ddr2 sdram so-dimms - continued - notes: 1. for details and notes, please refer to the re levant hynix component datasheet(hy5ps1g831(l)f). 2. 0 c g tcase g_\ c 3. g_\ c xg tcase gg`\ c parameter symbol ddr2-400 ddr2-533 unit note min max min max address and control input hold time tih 475 -375 - ps read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck auto-refresh to active/auto-refresh command period trfc 127.5 - 127.5 - ns row active to row active delay for 1kb page size trrd 7.5 - 7.5 - ns four activate window for 1kb page size tfaw 37.5 - 37.5 - ns four activate window for 2kb page size tfaw 50 - 50 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 -15 - ns auto precharge write recovery + precharge time tdal twr+trp - twr+trp - tck write to read command delay twtr 10 - 7.5 - ns internal read to precharge command delay trtp 7.5 7.5 ns exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non-read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al tck cke minimum pulse width (high and low pulse width) t cke 3 3 tck odt turn-on delay t aond 2222tck odt turn-on t aon tac(min) tac(max) +1 tac(min) tac(max) +1 ns odt turn-on(power-down mode) t aonpd tac(min)+2 2tck+tac (max)+1 tac(min)+2 2tck+tac (max)+1 ns odt turn-off delay t aofd 2.52.52.52.5tck odt turn-off t aof tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 ns odt turn-off (power-down mode) t aofpd tac(min)+2 2.5tck+tac (max)+1 tac(min)+2 2.5tck+tac (max)+1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih tis+tck+tih ns average periodic refresh interval trefi - 7.8 - 7.8 us 2 trefi - 3.9 - 3.9 us 3
rev. 1.2 / sep. 2005 16 1 200pin unbuffered ddr2 sdram so-dimms parameter symbol ddr2-667 unit note min max dq output access time from ck/ck tac -450 +450 ps dqs output access time from ck/ck tdqsck -400 +400 ps ck high-level width tch 0.45 0.55 tck ck low-level width tcl 0.45 0.55 tck ck half period thp min(tcl, tch) - ps clock cycle time, cl=x tck 3000 8000 ps dq and dm input setup time (differential strobe) tds 100 - ps 1 dq and dm input hold time (differential strobe) tdh 175 - ps 1 control & address input pulse width for each input tipw 0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - tck data-out high-impedance time from ck/ck thz - tac max ps dqs low-impedance time from ck/ck tlz(dqs) tac min tac max ps dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max ps dqs-dq skew for dqs and associated dq signals tdqsq - 240 ps dq hold skew factor tqhs - 340 ps dq/dqs output hold time from dqs tqh thp - tqhs - ps first dqs latching transition to associated clock edge tdqss - 0.25 + 0.25 tck dqs input high pulse width tdqsh 0.35 - tck dqs input low pulse width tdqsl 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - tck mode register set command cycle time tmrd 2 - tck write postamble twpst 0.4 0.6 tck write preamble twpre 0.35 - tck address and control input setup time tis 200 - ps address and control input hold time tih 275 - ps read preamble trpre 0.9 1.1 tck read postamble trpst 0.4 0.6 tck activate to precharge command tras 45 70000 ns active to active command period for 1kb page size products trrd 7.5 - ns four active window for 1kb page size products tfaw 37.5 - ns
rev. 1.2 / sep. 2005 17 1 200pin unbuffered ddr2 sdram so-dimms - continued - note : 1. for details and notes, please refer to the relevant hynix component datasheet(hy5ps1g831(l)f). 2. 0 c g tcase g_\ c zug_\ c xg tcase gg`\ c parameter symbol ddr2-667 unit note min max cas to cas command delay tccd 2 tck write recovery time twr 15 - ns auto precharge write recovery + precharge time tdal wr+trp - tck internal write to read command delay twtr 7.5 - ns internal read to precharge command delay trtp 7.5 ns exit self refresh to a non-read command txsnr trfc + 10 ns exit self refresh to a read command txsrd 200 - tck exit precharge power down to any non-read command txp 2 - tck exit active power down to read command txard 2 tck exit active power down to read command (slow exit, lower power) txards 7 - al tck cke minimum pulse width (high and low pulse width) t cke 3 tck odt turn-on delay t aond 22tck odt turn-on t aon tac(min) tac(max) +0.7 ns odt turn-on(power-down mode) t aonpd tac(min)+2 2tck+ tac(max)+1 ns odt turn-off delay t aofd 2.5 2.5 tck odt turn-off t aof tac(min) tac(max)+ 0.6 ns odt turn-off (power-down mode) t aofpd tac(min) +2 2.5tck+ tac(max)+1 ns odt to power down entry latency tanpd 3 tck odt power down exit latency taxpd 8 tck ocd drive mode output delay toit 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih ns average periodic refresh interval trefi -7.8us2 trefi - 3.9 us 3
rev. 1.2 / sep. 2005 18 1 200pin unbuffered ddr2 sdram so-dimms package outline 128mx64 - hymp112s64[p]8 front 67.60 2.00 min 4.00 +/-0.10 pin 1 pin 39 pin 41 pin 199 11.40 2.70 4.20 47.40 20.00 6.00 30.00 2.45 2.40 11.40 47.40 pin 2 pin 40 pin 42 pin 200 back 3.8 max 1.00 0.10 side note: 1. all dimension units are millimeters. 2. all outline dimensions and tolerances match up to the jedec standard. detail-b detail-b detail-a 0.45 0.03 0.60 0.20 0.15 detail of contacts a 2.55 detail of contacts b (front) 1.0 0.05 4.00 0.10 4.20 2.70 0.10 4.20 2.40 0.10 1.80 1.50 detail of contacts b (back)
rev. 1.2 / sep. 2005 19 1 200pin unbuffered ddr2 sdram so-dimms package outline 256mx64 - hymp325s64m[p]8 front 67.60 2.00 min 4.00 +/-0.10 pin 1 pin 39 pin 41 pin 199 11.40 2.70 4.20 47.40 20.00 6.00 30.00 2.45 2.40 11.40 47.40 pin 2 pin 40 pin 42 pin 200 back note: 1. all dimension units are millimeters. 2. all outline dimensions and tolerances match up to the jedec standard. side 3.8 max 1.00 0.10 0.45 0.03 0.60 0.20 0.15 detail of contacts a 2.55 detail of contacts b (front) 1.0 0.05 4.00 0.10 4.20 2.70 0.10 4.20 2.40 0.10 1.80 1.50 detail of contacts b (back) detail-b detail-b detail-a
rev. 1.2 / sep. 2005 20 1 200pin unbuffered ddr2 sdram so-dimms revision history revision history date 1.0 first version release - data sheet coverage is changed from an individual module part to a component based module family. feb. 2005 1.1 corrected module outline. mar. 2005 added vddl spec, corrected tds & tdh spec values. apr. 2005 1.2 added ddr2 667 speed bin part sep. 2005

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